PIC18C801T-I/L【PDF 41/319 页】IC MCU ROMLESS A/D PWM 84PLCC

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Sheet目录3891

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2001 Microchip Technology Inc.

Advance Information

DS39541A-page 135

PIC18C601/801

12.0

TIMER2 MODULE

The Timer2 module timer has the following features:

8-bit timer (TMR2 register)

8-bit period register (PR2)

Readable and writable (both registers)

Software programmable prescaler (1:1, 1:4, 1:16)

Software programmable postscaler (1:1 to 1:16)

Interrupt on TMR2 match of PR2

SSP module optional use of TMR2 output to

generate clock shift

Timer2 can be shut-off by clearing control bit TMR2ON

(T2CON register), to minimize power consumption.

Figure 12-1 is a simplified block diagram of the Timer2

module. The prescaler and postscaler selection of

Timer2 are controlled by this register.

12.1

Timer2 Operation

Timer2 can be used as the PWM time-base for the PWM

mode of the CCP module. The TMR2 register is read-

able and writable, and is cleared on any device RESET.

The input clock (FOSC/4) has a prescale option of 1:1,

1:4,

1:16,

selected

control

bits

T2CKPS1:T2CKPS0 (T2CON register). The match out-

put of TMR2 goes through a 4-bit postscaler (which

gives a 1:1 to 1:16 scaling inclusive) to generate a TMR2

interrupt (latched in flag bit TMR2IF, PIR registers).

The prescaler and postscaler counters are cleared

when any of the following occurs:

A write to the TMR2 register

A write to the T2CON register

Any device RESET (Power-on Reset, MCLR

Reset, or Watchdog Timer Reset)

TMR2 is not cleared when T2CON is written.

REGISTER 12-1:

T2CON REGISTER

Note:

Timer2 is disabled on POR.

U-0

R/W-0

—

TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0

bit 7

bit 0

bit 7

Unimplemented: Read as '0'

bit 6-3

TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits

0000

= 1:1 Postscale

0001

= 1:2 Postscale

1111

= 1:16 Postscale

bit 2

TMR2ON: Timer2 On bit

= Timer2 is on

= Timer2 is off

bit 1-0

T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits

= Prescaler is 1

= Prescaler is 4

= Prescaler is 16

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

- n = Value at POR

’1’ = Bit is set

’0’ = Bit is cleared

x = Bit is unknown

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